general description the DS2127 ultra3 lvd/se scsi terminator provides low-voltage differential (lvd)/single-ended (se) termi- nations for 14 scsi lines. through the voltage on the diff_cap pin, the device detects the types of drivers on the bus. if the device is connected in an lvd-only bus, the DS2127 provides lvd termination. if any sin- gle-ended devices are connected to the bus, the DS2127 uses se termination. if any high-voltage differ- ential (hvd) devices are connected to the bus, the DS2127 isolates itself from the scsi bus. the mode change has a built-in delay that is determined by an integrated spi-3 mode change filter/delay. the termi- nating resistors can also be disconnected from the bus by asserting the iso pin. for the lvd termination, the DS2127 provides 14 pre- cisely trimmed resistors. each resistor is biased with two current sources to a fail-safe state. for se termina- tion, the DS2127 provides 14 precision 110 ? resistors and one regulator for active-negation bias. applications scsi array backplane scsi cables features ? fully compliant with ultra2, ultra3, ultra160, and ultra320 scsi standards ? provides lvd/se termination for 14 signal pairs ? auto-selection of lvd or se termination ? 5% tolerance on se and lvd termination resistance ? low 3pf power-down capacitance ? built-in mode-change filter/delay ? on-board thermal-shutdown circuitry ? scsi bus hot-plug compatible ? fully supports actively negated se scsi signals DS2127 ultra3 lvd/se scsi 14-line terminator ______________________________________________ maxim integrated products 1 r13n r13p r12n r12p r11n r11p r10n r10p r9n r9p r8n r8p r2p r2n r3p r3n r4p r4n r5p r5n r6p r6n r7p r7n 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 lqfp gnd se lvd hs_gnd hs_gnd hs_gnd hs_gnd hs_gnd hs_gnd diff_cap diffsens iso 25 26 27 28 29 30 31 32 33 34 35 36 12 11 10 9 8 7 6 5 4 3 2 1 r1n r1p v ref hs_gnd hs_gnd hs_gnd hs_gnd hs_gnd hs_gnd tpwr r14n r14p DS2127 top view pin configuration ordering information rev 0; 7/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package top mark DS2127 0? to +70 c 48 lqfp DS2127
DS2127 ultra3 lvd/se scsi 14-line terminator 2 _____________________________________________________________________ absolute maximum ratings electrical characteristics (tpwr = v tpwr(min) to v tpwr(max) , t a = 0? to +70?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on all pins relative to ground ......-0.3v to +6.0v v ref continuous output current....................................?00ma operating temperature range...............................0? to +70? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? soldering temperature .......................................see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units lvd 2.7 3.3 5.5 tpwr operating supply range (note 1) v tpwr se 4 5.0 5.5 v tpwr supply current i tpwr_lvd lvd scsi mode 32 i tpwr_se se scsi mode 10 ma tpwr supply current (all lines open) i tpwr_iso iso mode (terminators disabled) 750 ? lvd termination (applies to each line pair, 1 to 14 in lvd mode) differential-mode termination resistance r dm 100 110 ? common-mode termination resistance r cm r p and r n shorted together (v cm(max) = 2v, v cm(min) = 0.5v) 110 165 ? differential-mode bias v dm all lines open 100 125 mv common-mode bias v cm r p and r n shorted together (note 1) 1.15 1.25 1.35 v se termination (applies to single-ended terminators, 1 to 14 in se mode) single-ended mode termination resistance r se r se = (v lx - 0.2) / i lx , where v lx = voltage at terminator pin with pin unloaded and i lx = current for each terminator pin with the pin forced to 0.2v 104.5 110 115.5 ? signal level at 0.2v, all lines low -21 -24 -25.4 termination current i se signal level at 0.5v -18 -22.4 ma se voltage reference v ref 2.7 2.85 3.0 v pin leakage with iso high 400 na single-ended gnd resistance r gnd measured at r p pins, i = 10ma 20 60 ? terminator pin capacitance terminator pin capacitance c in with iso high (note 2) 3 pf v ref regulator 1.25v regulator output voltage v ref_lvd 0.5v v cm 2.0v, v cm applied to all r p and r n lines simultaneously 1.15 1.25 1.35 v 1.25v regulator short-circuit source current i source v ref = 0v -375 -700 -1000 ma 1.25v regulator short-circuit sink current i sink v ref = 3.3v 170 300 700 ma
DS2127 ultra3 lvd/se scsi 14-line terminator _____________________________________________________________________ 3 note 1: all voltages are referenced to ground. note 2: guaranteed by design and not production tested. electrical characteristics (continued) (tpwr = v tpwr(min) to v tpwr(max) , t a = 0? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units v ref regulator 1.25v regulator line regulation v ref unloaded; vary tpwr from 2.7v to 5.5v 1.0 2.5 % 2.85v regulator 2.7 2.85 3.0 v 2.85v regulator short-circuit source current v ref = 0v -375 -700 -1000 ma 2.85v regulator short-circuit sink current v ref = 3.3v 170 300 700 ma 2.85v regulator line regulation v ref unloaded; vary tpwr from 2.7v to 5.5v 1.0 2.5 % diffsens output diffsens driver output voltage v dso -5ma i diffsens 50? 1.2 1.4 v diffsens driver source current i dsh v diffsens = 0v -15 -5 ma diffsens driver sink current i dsl v diffsens = 2.75v 100 200 ? i leak, low with iso high, |v diffsens | = 0.3v -3 +1 diffsens leakage i leak, high with iso high, |v diffsens - v tpwr | = 0.3v 1 3 ? thermal shutdown thermal-shutdown threshold for increasing temperature 130 ? thermal-shutdown hysteresis 10 ? mode change delay/filter mode change delay t delay 0.66 1.25 2.00 ms logical signals (iso) input low voltage v il -0.3 +0.8 v input high voltage v ih 2.0 tpwr + 0.3 v input current i il v cc = 3.3v -30 -10 ? status bits (lvd, se) source current i oh v cc = 3.3v, v load = 2.4v -4 -6 ma sink current i ol v cc = 3.3v, v load = 0.4v 2 5 ma diff_cap input current il v il = -0.3v -1 +1 ? diff_cap se operating range v seor -0.3 +0.5 v diff_cap lvd operating range v lvdor 0.7 1.9 v diff_cap hvd operating range v hvdor 2.4 v tpwr + 0.3 v
DS2127 ultra3 lvd/se scsi 14-line terminator 4 _____________________________________________________________________ pin description pin name function 1, 2, 11?4, 37?8 r_ _ p, r_ _ n signal termination. connect to scsi bus signal lines. asserting iso removes the terminators from the scsi bus. r_ _ p pins are the ground line for se operation and the positive lines in differential mode. r_ _ n pins are the signal lines in se operation and the negative lines in differential mode. 3 tpwr termination power. connect to the scsi termpwr line and decouple with a ceramic 2.2? capacitor. 4?, 28?3 hs_gnd heat-sink ground. internally connected to the mounting pad. these pins must be connected to ground. these pins should be connected to a ground plane with the layout optimized for heat transfer. 10 v ref regulator output voltage. this must be decoupled with a 4.7? capacitor. asserting iso floats this output. a high-frequency capacitor (0.1?) should also be placed on the v ref pin in applications that use fast rise/fall-time drivers. 25 gnd signal ground 26 se se mode indicator. a high state indicates se mode detected on scsi bus. 27 lvd lvd mode indicator. a high state indicates lvd mode detected on scsi. 34 diff_cap diffsense capacitor. connect a 0.1? capacitor for the diffsense filter. input to detect the type of device (differential or single-ended) on the scsi bus. 35 diffsens diffsense. output to drive the scsi bus diffsens line. 36 iso isolation input. when pulled high, terminating resistors and biasing current sources are removed from the scsi bus. when not connected to ground, the pin has a 10? current source pulling the pin to the high state. 2.15v 0.6v thermal shutdown 1.30v diff_cap iso 2.15v 1.30v 1.25v (lvd) r1n r1p r14n r14p v ref 0.6v diffsens 2.85v (se) lvd se hvd lvd se hvd lvd se lvd se control logic delay/ filter bandgap refgen and trim 10 a 52 ? 52 ? 52 ? 52 ? 110 ? 110 ? 124 ? 124 ? se all switches up hvd/iso all switches center lv d all switches down DS2127 figure 1. block diagram
detailed description the DS2127 provides dual-mode active terminators with auto-switching se and lvd termination for 14 scsi lines. the diffsense signal performs mode detection and selection. in lvd mode, the termination configuration is a y-type terminator with a 105 ? differential resistance and a 150 ? common-mode resistance. the termination resis- tor is biased with two current sources and the common- mode node is connected to a 1.25v voltage regulator. a fail-safe bias of 112mv is maintained when no drivers are connected to the scsi bus. in se mode, each negative signal input pin is connect- ed to 2.85v through a 110 ? resistor. in hvd mode, the termination resistors are isolated from the scsi bus and the resistor pins are left floating. the voltage regulator is powered down and the v ref pin is in a high-impedance state. the diff_cap pin is connected to the scsi diffsense line and monitors the voltage to determine the proper operating mode of the device. any diffsense voltage below 0.5v indicates single ended; any diffsense volt- age between 0.7v and 1.9v is lvd, and above 2.4v is an hvd scsi. on power-up, the DS2127 assumes se mode. if the voltage on the diff_cap is between 0.7v and 1.9v, the device waits t delay before entering the lvd mode. the delay is the same when changing modes. a new mode change can start at any time after a previous mode change has been detected. typically, four DS2127s are used in a scsi bus seg- ment. on two chips, the diff_cap inputs at each end of the bus should be connected together. there should be a 50hz noise filter implemented on diff_cap at each end of the bus, as close as possible to the diff_cap pins. this filter consists of a 20k ? resistor between the diffsens and diff_cap pins, and a 0.1? capacitor from diff_cap to gnd. see figure 2 for the typical operating circuit. when iso is connected to tpwr, the termination pins are isolated from the scsi bus and v ref becomes inactive, and the device is in a low-power state. during thermal shutdown, the termination pins are isolated from the scsi bus and v ref becomes high impedance. the diffsens driver is shut down during either of these two events. lvd and se signals indicate whether the scsi bus segment is in lvd or se mode. chip information transistor count: 8114 cmos and 87 bipolar process: bicmos substrate connected to ground thermal information thermal resistance (junction-to-ambient): ja = +29?/w thermal resistance (junction-to-case): jc = +10?/w DS2127 ultra3 lvd/se scsi 14-line terminator _____________________________________________________________________ 5 tpwr iso tpwr iso diff_cap diffsens 4.7 f 0.1 f 4.7 f 2.2 f 2.2 f 2.2 f 2.2 f 0.1 f diffsens 20k ? 20k ? v ref v ref v ref v ref diffsens diffsens iso gnd tpwr iso gnd tpwr diffsens diff_cap diff_cap diff_cap 4.7 f 4.7 f data lines (8) + parity data lines (4) + parity control lines (9) data lines (4) gnd gnd figure 2. typical operating circuit
DS2127 ultra3 lvd/se scsi 14-line terminator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)
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